High voltage pmos (hvpmos) transistor with a composite drift region and manufacture method thereof

ABSTRACT

In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.

RELATED APPLICATIONS

This application claims the benefit of Chinese Patent Application No.201310194265.5, filed on May 22, 2013, which is incorporated herein byreference in its entirety.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices, and moreparticularly to a high voltage PMOS (HVPMOS) transistor with a compositedrift region formed by implantation, and an associated manufacturingmethod.

BACKGROUND

A switched-mode power supply (SMPS), or a “switching” power supply, caninclude a power stage circuit and a control circuit. When there is aninput voltage, the control circuit can consider internal parameters andexternal load changes, and may regulate the on/off times of the switchsystem in the power stage circuit. In this way, the output voltageand/or the output current of the switching power supply can bemaintained as substantially constant. Therefore, the selection anddesign of the particular control circuitry and approach, as well as thetypes of circuit components, can be important to the overall performanceof the switching power supply. For example, HVPMOS transistors can beemployed as switching devices in an SMPS.

SUMMARY

In one embodiment, a high voltage PMOS (HVPMOS) transistor can include:(i) a P-type substrate; (ii) a deep N-type well in the P-type substrate;and (iii) a composite drift region in the deep N-type well, where thecomposite drift region comprises an increasing doping concentration andan increasing junction depth along a horizontal direction of the deepN-type well.

In one embodiment, method of making an HVPMOS transistor, can include:(i) providing a P-type substrate; (ii) implanting N-type dopants in theP-type substrate; (iii) dispersing the implanted N-type dopants in theP-type substrate to form a deep N-type well; (iv) implanting P-typedopants of different doping concentrations in the deep N-type well alonga horizontal direction of the deep N-type well; and (v) dispersing theimplanted P-type dopants to form a composite drift region having anincreasing doping concentration and an increasing junction depth alongthe horizontal direction of the deep N-type well.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow diagram of an example method of making an HVPMOStransistor using a BCD process.

FIG. 2 is a cross-section diagram of an example HVPMOS transistor formedby a BCD process.

FIG. 3 is a flow diagram of an example method of making an HVPMOStransistor with a composite drift region, in accordance with theembodiments of the present invention.

FIG. 4 is a flow diagram of an example method of making a compositedrift region of an HVPMOS transistor, in accordance with embodiments ofthe present invention.

FIG. 5 is a flow diagram of an example method of making an HVPMOStransistor with a single oxide layer and a composite drift region, inaccordance with embodiments of the present invention.

FIG. 6 is a cross-section diagram of an example HVPMOS transistor with asingle oxide layer and a composite drift region based on the flowdiagram of FIG. 5, and in accordance with embodiments of the presentinvention.

FIG. 7 is a flow diagram of another method of making an HVPMOStransistor with a single oxide layer and a composite drift region, inaccordance with embodiments of the present invention.

FIG. 8 is a cross-section diagram of an example HVPMOS transistor with asingle oxide layer and a composite drift region based on the flowdiagram of FIG. 7, and in accordance with embodiments of the presentinvention.

FIG. 9 is a flow diagram of an example method of making an HVPMOStransistor with a composite oxide layer and a composite drift region, inaccordance with the embodiments of the present invention.

FIG. 10 is a flow diagram of an example method of making an HVPMOStransistor with a composite oxide layer and a composite drift region, inaccordance with the embodiments of the present invention.

FIG. 11 is a cross-section diagram of an example HVPMOS transistor witha composite oxide layer and a composite drift region based on the flowdiagrams of FIGS. 9 and 10, and in accordance with embodiments of thepresent invention.

FIG. 12 is a flow diagram of an example method of making an HVPMOStransistor with a composite oxide layer and a composite drift region, inaccordance with embodiments of the present invention.

FIG. 13 is a cross-section diagram of an example HVPMOS transistor witha composite oxide layer and a composite drift region based on the flowdiagram of FIG. 12, and in accordance with embodiments of the presentinvention.

FIG. 14 is a flow diagram of an example method of making a single oxidelayer and a drift region, in accordance with embodiments of the presentinvention.

DETAILED DESCRIPTION

Reference may now be made in detail to particular embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. While the invention may be described in conjunction with thepreferred embodiments, it may be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents that may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it may be readilyapparent to one skilled in the art that the present invention may bepracticed without these specific details. In other instances, well-knownmethods, procedures, processes, components, structures, and circuitshave not been described in detail so as not to unnecessarily obscureaspects of the present invention.

A high voltage PMOS transistor (HVPMOS) can be employed as a powerdevice or switch in a switched-mode power supply (SMPS) or a “switching”power supply. In some cases, an HVPMOS transistor can be used inconjunction with a laterally diffused metal oxide semiconductor (LDMOS)transistor (e.g., an N-LDMOS) in a switching regulator. In one example,an HVPMOS transistor can be made by a standard BCD (Bipolar-CMOS-DMOS)process. There are typically four terminals for a HVPMOS: gate, body,source, and drain. When a voltage between the source and gate V(sg) islower than a threshold voltage (Vth) of the HVPMOS transistor, theHVPMOS can be turned off to prevent a high voltage at the source frompassing through the transistor. Conversely, when the voltage V(sg)between the source and gate is higher than threshold voltage Vth, theHVPMOS transistor can be turned on to conduct current between the sourceand drain. Thus, an HVPMOS transistor can be employed as a switch inmany applications.

Breakdown voltage (BV) and on resistance (Ron) are important parametersfor a HVPMOS transistor. Breakdown voltage BV can represent a maximumreverse voltage that can be accommodated by such powerdevices/transistors. Therefore, the higher the breakdown voltage, thebetter the power device (e.g., HVPMOS transistor) can perform, such asin a switching regulator application. Also, the lower the on resistance(Ron), the better the power device can decrease power losses across thepower device. Referring now to FIG. 1, shown is a flow diagram of anexample method of making an HVPMOS transistor using a BCD process. Alsoshown in FIG. 2 is a cross-section diagram of an example HVPMOStransistor formed by such a BCD process.

At S1, a P-type silicon substrate (PSUB) can be provided. At S2, N-typedopants can be implanted and dispersed to form a deep N-type well(DNWELL). For example, N-type impurities or dopants (e.g., phosphorus,etc.) can be implanted in the PSUB and dispersed to form a DNWELL as thechannel of an HVPMOS transistor. At S3, P-type impurities or dopants(e.g., boron, etc.) can be implanted and dispersed to form a P-type well(Pwell). For example, P-type impurities can be implanted in the DNWELL,and then may be disbursed to form a Pwell as a “drift” region of theHVPMOS transistor.

At S4, an oxide layer can be grown. For example, the oxide can be grownover PSUB on a portion of DNWELL in which a Pwell has been formed. AtS5, polysilicon can be deposited, e.g., on oxide to form a gate of theHVPMOS transistor. At S6, P+ dopants and N+ dopants to form the body,source, and drain regions and/or contact points, for the HVPMOStransistor. For example, on a portion of DNWELL that is not overlappedby oxide, P+ impurity can be implanted to form a source, and N+ impuritycan be implanted to form a diffusion region for a body contact. Also,the drain can be formed by implanting P+ impurity on a portion of Pwellthat is not overlapped by the oxide.

In some approaches, Pwell employed as the drift region can be formed byimplanting and dispersing P-type impurity to make an HVPMOS transistorby a BCD process. However, with a BCD processing approach, it may bedifficult to control the implantation dosage of the Pwell, and HVPMOStransistor performance limitations can result. For example, if theimplantation dosage is too large, the breakdown voltage of thetransistor may be decreased. Also, if the implantation dosage is toosmall, the on resistance of the HVPMOS transistor may be increased.

In one embodiment, method of making an HVPMOS transistor, can include:(i) providing a P-type substrate; (ii) implanting N-type dopants in theP-type substrate; (iii) dispersing the implanted N-type dopants in theP-type substrate to form a deep N-type well; (iv) implanting P-typedopants of different doping concentrations in the deep N-type well alonga horizontal direction of the deep N-type well; and (v) dispersing theimplanted P-type dopants to form a composite drift region having anincreasing doping concentration and an increasing junction depth alongthe horizontal direction of the deep N-type well.

Referring now to FIG. 3, shown is a flow diagram of an example method ofmaking an HVPMOS transistor with a composite drift region, in accordancewith the embodiments of the present invention. This manufacturing methodof an HVPMOS transistor with a composite drift region will be describedin conjunction with the example transistor devices shown in FIGS. 6, 8,11, and 13. At S11, a P-type substrate (PSUB) can be provided. At S12,N-type dopants (e.g., phosphorus, etc.) can be implanted in the P-typesubstrate, and then dispersed in the P-type substrate to form a deepN-type well (DNWELL), which can be configured as the channel of theHVPMOS transistor.

At S13, P-type dopants (e.g., boron, etc.) of different dopingconcentrations along a horizontal direction (e.g., left to right in FIG.6) can be implanted in the deep N-type well (DNWELL), and then dispersedto form corresponding (adjacent) drift regions. For example, the dopingconcentrations and junction depths of the drift regions can be increasedin sequence along the horizontal direction, with each drift region tothe right having a higher doping concentration and junction depth thanthe drift region immediately to its left. In this fashion, a compositedrift region of progressively increased doping concentration andjunction depth can be configured along the horizontal direction of thedeep N-type well (DNWELL). In particular embodiments, an HVPMOStransistor with a composite drift region can be formed, e.g., using S11to S13, and which can include a P-type substrate, a deep N-type well inthe P-type substrate, and a composite drift region with progressivelyincreased doping concentration and junction depth in the deep N-typewell along the horizontal direction.

Therefore, the composite drift region of the HVPMOS transistor does notutilize a conventional drift region that is formed by only onceimplanting single P-type dopants, such as in a BCD process. In certainembodiments, P-type dopants can be implanted several (e.g., at leasttwo) times, and dispersed to form corresponding adjacent drift regionsof the composite drift region. Also, the performance of the compositedrift region can be regulated by adjustment of the doping concentrationand/or junction depth of the drift region, such as at one or more of thedrift region formation steps. Further, implantation dosage of thecomposite drift region can be more accurately controlled for an HVPMOStransistor in particular embodiments.

The composite drift region can be configured to be in the deep N-typewell, and the surface of the deep N-type well that is adjacent to theP-type substrate may have better surface homogeneity, as compared toother approaches. Therefore, the intrinsic breakdown performance of anHVPMOS transistor of particular embodiments can be improved relative tothe breakdown performance that can occur on a more conventional devicesurface. In addition, along the horizontal direction of the deep N-typewell, the doping concentration of the drift region (e.g., at the farleft) can be less, and the doping concentration of the remaining driftregions (e.g., in going from left to right in FIG. 6) can beprogressively increased. Further, the doping concentration of thecomposite drift region can be still much higher than conventionalapproaches in order to decrease the on resistance of the HVPMOStransistor.

Referring now to FIG. 4, shown is a flow diagram of an example method ofmaking a composite drift region of an HVPMOS transistor, in accordancewith embodiments of the present invention. In this example, the examplemethod of forming the composite drift region in step S13 can include thefollowing steps. At S131, P-type dopants can be implanted in the deepN-type well, and may be disbursed at a first time to form a first driftregion (Pwell1) with a lowest doping concentration and junction depth.For example, the first drift region (Pwell1) can be formed beforeformation of a single oxide layer. This can improve the conductionperformance of the HVPMOS transistor, and the gate can be formed on thefirst drift region (Pwell1). This can improve the breakdown voltage dueto the lowest doping concentration first drift region (Pwell1)preventing surface breakdown of the HVPMOS transistor when a highervoltage is supplied on the gate.

At S132, adjacent to the side wall of first drift region (Pwell1),P-type dopants of different doping concentrations can be implanted inthe deep N-type well from left to right along a horizontal direction.This can be done in sequence at a corresponding second time through ann^(th) time (e.g., second, third, fourth, . . . n^(th)), and the P-typedopants can be dispersed to form a second drift region (Pwell2) throughan n^(th) drift region with progressively increasing dopingconcentrations and junction depths along the horizontal direction. Forexample, “n” can be an integer of at least two.

Although the doping concentration of first drift region Pwell1 is lower,the doping concentration of each of second drift region Pwell2 to then^(th) drift region can be progressively increased. This can alsoincrease the doping concentration of the composite drift region todecrease the on resistance of the HVPMOS transistor in particularembodiments. In the examples discussed herein, n is two or three tofacilitate the description. However, any suitable number of driftregions or value of “n” (of at least two) can be accommodated inparticular embodiments, and thus may not limit the number of driftregions of the composite drift region. The particular number of driftregions can be adjusted for a given application to form a suitablecomposite drift region.

Referring now to FIG. 5, shown is a flow diagram of an example method ofmaking an HVPMOS transistor with a single oxide layer and a compositedrift region, in accordance with embodiments of the present invention.In this example, after formation of the composite drift region(including first and second drift regions), oxide material can bedeposited on the composite drift region to form a single oxide layer, asshown in S14.

In one embodiment, an HVPMOS transistor can include: (i) a P-typesubstrate; (ii) a deep N-type well in the P-type substrate; and (iii) acomposite drift region in the deep N-type well, where the compositedrift region comprises an increasing doping concentration and anincreasing junction depth along a horizontal direction of the deepN-type well. FIG. 6 shows a cross-section diagram of an example HVPMOStransistor with a single oxide layer and a composite drift region basedon the flow diagram of FIG. 5, and in accordance with embodiments of thepresent invention.

Referring now to FIG. 7, shown is a flow diagram of another examplemethod of making an HVPMOS transistor with a single oxide layer and acomposite drift region, in accordance with embodiments of the presentinvention. After formation of the first drift region in S131, oxidematerial can be deposited to form a single oxide layer at S14. At S132,on a surface of a predetermined region of the composite drift region,the second drift region and third drift regions, etc., can be formed toform the composite drift region.

Referring now to FIG. 8, shown is a cross-section diagram of an exampleHVPMOS transistor with a single oxide layer and a composite drift regionbased on the flow diagram of FIG. 7, and in accordance with embodimentsof the present invention. In this example, n=3, and three drift regions(e.g., Pwell1, Pwell2, and Pwell3) can form the composite drift region.Here, in step S14 of FIG. 7, the single oxide layer can be formed afterthe first drift region is formed. However, the sequence of steps of thesingle oxide layer and the second drift region through the n^(th) driftregions can vary. In accordance with the steps from S11 to S14, theHVPMOS transistor can include a single oxide layer on the compositedrift region, as shown in FIG. 8.

Furthermore, with reference to FIGS. 6 and 8, after S14, the examplemethod of making an HVPMOS transistor with a composite drift region canalso include depositing polysilicon substantially on the single oxidelayer formed on the first drift region (Pwell1) of the composite driftregion of a lowest doping concentration and junction depth, to form thegate of the HVPMOS transistor. Also, P+ dopants can be implanted to formthe source, and N+ dopants can be implanted to form or allow for thebody contact for the HVPMOS transistor, in a remaining region of thedeep N-type outside of the composite drift region. Also, P+ dopants canbe implanted in the n^(th) drift region (e.g., Pwell3) of the highestdoping concentration and junction depth that is adjacent to the singleoxide layer to form the drain of the HVPMOS transistor.

In this way, an HVPMOS transistor of particular embodiments can includea gate on a single oxide layer that is on a composite drift region, asdiscussed herein. Also, the source and body diffusion regions forcontacting can be formed in a remaining region of the deep N-type welloutside or excluding the composite drift region. The drain can be formedin the drift region of highest doping concentration and junction depthof the composite drift region that is adjacent to the single oxidelayer.

Referring now to FIG. 9, shown is a flow diagram of an example method ofmaking an HVPMOS transistor with a composite oxide layer and a compositedrift region, in accordance with the embodiments of the presentinvention. After formation of the composite drift region including thefirst and second drift regions, at S16, oxide material can be depositedon the composite drift region at least twice to form adjacent firstoxide layer (Oxide1) and second oxide layer (Oxide2) from left to rightin sequence (see, e.g., FIG. 11) to form a composite oxide layer. Inthis particular example, the first oxide layer (Oxide1) can be formed onthe first drift region, and the second oxide layer (Oxide2) can beformed on the second drift region.

Referring now to FIG. 10, shown is a flow diagram of an example methodof making an HVPMOS transistor with a composite oxide layer and acomposite drift region, in accordance with the embodiments of thepresent invention. After formation of the first drift region, at S161,oxide material can be deposited on the first drift region to form thefirst oxide layer (Oxide1). In this example, at S132, the second driftregion can be formed. At S162, oxide material can be deposited on thesecond drift region to form the second oxide layer (Oxide2).

Referring now to FIG. 11, shown is a cross-section diagram of an exampleHVPMOS transistor with a composite oxide layer and a composite driftregion based on the flow diagrams of FIGS. 9 and 10, and in accordancewith embodiments of the present invention. In this example, the firstoxide layer and the second oxide layer are adjacent and arranged insequence from left to right in a horizontal direction to form thecomposite oxide layer.

Referring now to FIG. 12, shown is a flow diagram of an example methodof making an HVPMOS transistor with a composite oxide layer and acomposite drift region, in accordance with embodiments of the presentinvention. In this example, after formation of the first drift region,oxide material can be deposited on predetermined regions of thecomposite drift region three times to form the first oxide layer(Oxide1), the second oxide layer (Oxide2), and the third oxide layer(Oxide3) adjacent in sequence from left to right to form the compositeoxide layer. For example, the first oxide layer (Oxide1) can be on thefirst drift region, the second oxide layer (Oxide2) can be on the seconddrift region, and the third oxide layer (Oxide3) can be on the thirddrift region.

Referring now to FIG. 13, shown is a cross-section diagram of an exampleHVPMOS transistor with a composite oxide layer and a composite driftregion based on the flow diagram of FIG. 12, and in accordance withembodiments of the present invention. Based on the implanting process ofS132, the second and third drift regions can be formed together with thefirst drift region to form the composite drift region of Pwell1, Pwell2,and Pwell3.

Thus, an HVPMOS transistor in particular embodiments can also include acomposite oxide layer on the composite drift region, which can includeat least two adjacent oxide layers from left to right in sequence. Also,thickness of the oxide layers (e.g., Oxide1, Oxide2, Oxide3, etc.) inthe composite oxide layer can be identical, or substantially the same,in some cases. In other cases, the thicknesses of the oxide layers(e.g., Oxide1, Oxide2, Oxide3, etc.) can be progressively increased fromleft to right along the horizontal direction of the deep N-type well, tocoincide with the doping concentration and the junction depth of thedrift regions. In particular embodiments, the composite oxide layer canbe formed by multiple single oxide layers or oxide regions. The numberof the single oxide “layers” can be adjusted in the manufacture of anHVPMOS transistor according for a given application.

Referring now to FIG. 14, shown is a flow diagram of an example methodof making a single oxide layer and a drift region, in accordance withembodiments of the present invention. The composite oxide layer caninclude at least two single oxide layers or regions (e.g., Oxide1 andOxide2), and the composite drift regions can include at least two driftregions. The formation of single oxide layers (Oxide1 and Oxide2) can berespectively labeled as A and B, and the formation of remaining driftregions other than the formation of first drift region (Pwell1) can belabeled as C. In particular embodiments, the sequence of steps A to Ccan be variable to change or optimize performance of breakdown voltageand/or on resistance of an HVPMOS transistor.

Furthermore, with reference to FIGS. 11 and 13, after S16, the examplemethod of making an HVPMOS transistor with a composite drift region canalso include depositing polysilicon substantially on the single oxidelayer formed on the first drift region (Pwell1) of the composite driftregion of a lowest doping concentration and junction depth to form thegate of the HVPMOS transistor. Also, P+ dopants can be implanted to formthe source, and N+ dopants can be implanted to form or allow for thebody contact for the HVPMOS transistor, in a remaining region of thedeep N-type outside of the composite drift region. Also, P+ dopants canbe implanted in the n^(th) drift region of the highest dopingconcentration and junction depth that is adjacent to the single oxidelayer to form the drain of the HVPMOS transistor.

When the thickness of the single oxide layers or regions (e.g., Oxide1,Oxide2, and Oxide3) is the same, the composite oxide layer of ahomogeneous thickness between the gate and drain can be configured toaccommodate the voltage drop between the gate and drain. However, theportion of the composite oxide layer or region adjacent to the gate cansupport a lower voltage drop, while the portion of the composite oxidelayer adjacent to the drain can support a higher voltage drop. Inparticular embodiments, the thickness of the single oxide layers orregions (e.g., Oxide1, Oxide2, and Oxide3) can be progressivelyincreased to form a composite oxide layer of progressively increasedthickness between the gate and drain from left to right along thehorizontal direction of the deep N-type well. This can be similar to thevariation of the composite drift region of progressively increaseddoping concentrations and junction depths, to accommodate an increasedvoltage drop between the gate and drain.

The embodiments were chosen and described in order to best explain theprinciples of the invention and its practical applications, to therebyenable others skilled in the art to best utilize the invention andvarious embodiments with modifications as are suited to the particularuse contemplated. It is intended that the scope of the invention bedefined by the claims appended hereto and their equivalents.

1.-15. (canceled)
 16. A method of making a high voltage MOS (HVMOS)transistor, the method comprising: a) providing a semiconductor layer;b) implanting first doping type dopants of different dopingconcentrations in said semiconductor layer along a first directionextending from a gate contact to a drain contact of said HVMOStransistor; c) dispersing said implanted first doping type dopants toform a composite drift region having an increasing doping concentrationand an increasing junction depth along said first direction; d) forminga gate dielectric layer on said semiconductor layer; and e) forming acomposite oxide layer on said composite drift region, wherein saidcomposite oxide layer comprises at least two adjacent single oxidelayers having a same thickness or an increasing thickness along saidfirst direction.
 17. The method of claim 16, wherein said forming saidcomposite drift region comprises: a) implanting and dispersing, at afirst time, first doping type dopants in said semiconductor layer toform a first drift region having a lowest doping concentration and alowest junction depth; and b) implanting and dispersing, beginning froma side wall of said first drift region and from at a second time to ann^(th) time in sequence, first doping type dopants of increasing dopingconcentrations along said first direction, to form adjacent second ton^(th) drift regions having progressively increasing dopingconcentrations and junction depths, wherein n is an integer of at leasttwo.
 18. The method of claim 17, further comprising forming a compositeoxide layer by depositing oxide material on said composite drift regionat least twice to form at least two adjacent single oxide layers alongsaid first direction.
 19. The method of claim 18, wherein: a) formingsaid composite oxide layer occurs after forming said first drift region;and b) forming said composite oxide layer occurs before or after formingsaid second drift region through said n^(th) drift region.
 20. Themethod of claim 18, wherein said at least two adjacent single oxidelayers comprises a same thickness or an increasing thickness along saidfirst direction.
 21. The method of claim 18, further comprising: a)forming said gate contact by depositing polysilicon on a gate dielectriclayer of said high voltage MOS transistor and a portion of saidcomposite oxide layer that is on said first drift region; b) forming afirst doping type source contact and a second doping type body contactby implanting first doping type dopants and second doping type dopantsseparately in a portion of said semiconductor layer that is outside ofsaid composite drift region; and c) forming said drain contact byimplanting first doping type dopants in a portion of said n^(th) driftregion adjacent to said composite oxide layer.
 22. The method of claim16, wherein providing a semiconductor layer comprises providing asubstrate having said first doping type, and forming a deep well havinga second doping type in said substrate, said composite drift region islocated in said deep well.